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82212nk 20120821-s00001/d1510sypc 20101025-s00003 no.a1868-1/36 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. lv8414cs overview the lv8414cs is a motor driver ic that incorporates two channels of pwm constant-current control micro-step drivers. miniaturization using the wafer level package (w lp) makes the ic ideally suited for driving the stepping motors used to control the lenses in digital still came ras, cell phone camera modules and other such devices. features ? two channels of 256-division micro-step drivers ? excitation step proceeds only by step signal input ? peak excitation current switchable to one of 16 levels ? serial data control using i 2 c interface ? built-in thermal protection circuit ? low supply voltage protection circuit incorporated ? on-chip photo sensor drive transistors ? on-chip schmitt buffer specifications maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit maximum supply voltage 1 v m max 6.0 v maximum supply voltage 2 v cc max 6.0 v output peak current i o peak ch1 to 4 t ? 10ms, on-duty ? 20% 600 ma continuous output current 1 i o max1 ch1 to 4 400 ma continuous output current 2 i o max2 pi 30 ma allowable power dissipation pd max *mounted on a specified board. 1.0 w operating temperature topr -30 to +85 ? c storage temperature tstg -55 to +150 ? c * specified circuit board : 40mm ? 50mm ? 0.8mm, glass epoxy four-layer board. bi-cmos ic microstep driver motor driver ic orderin g numbe r : ena1868a
lv8414cs no.a1868-2/36 allowable operating conditions at ta = 25 ? c parameter symbol conditions ratings unit operating supply voltage range1 v m op 2.5 to 5.5 v operating supply voltage range2 v cc op 2.5 to 5.5 v logic input voltage v in 0 to v cc +0.3 v clk input frequency fin clk1 to 2 100 khz electrical characteristics at ta = 25c, v m = 5.0v, v cc = 3.3v parameter symbol conditions ratings unit min typ max standby mode current drain istn ena = "l" 1.0 ? a vm current drain i m ena = "h", im1 + im2, with no load 50 100 200 ? a v cc current drain i cc ena = "h" 0.75 1.5 3.0 ma v cc low-voltage cutoff voltage vthv cc 2.0 2.25 2.5 v low-voltage hysteresis volt age vthhys 100 150 200 mv thermal shutdown temperature tsd design guarantee value * 160 180 200 ? c thermal hysteresis width ? tsd design guarantee value * 10 30 50 ? c micro-step driver logic pin internal pull-down resistance rin ena, clk1 to 2, fr1 to 2 50 100 200 k ? logic pin input current iinl v in = 0, ena, clk1 to 2, fr1 to 2 1.0 ? a iinh v in = 3.3v, ena, clk1 to 2, fr1 to 2 16.5 33 66 ? a logic high-level voltage vinh ena, scl, sda, clk1 to 2, fr1 to 2 0.6 ? v cc v logic low-level voltage vinl ena, scl, sda, clk1 to 2, fr1 to 2 0.2 ? v cc v output on-resistance ronu i o = 100ma, upper on resistance 0.38 ? rond i o = 100ma, lower on resistance 0.22 ? ron i o = 100ma, sum of upper- and lower-side on resistance 0.6 1.0 ? output leakage current i o leak 1.0 ? a diode forward voltage vd i d = -100ma 0.45 0.75 1.1 v chopping frequency fchop00 280 400 520 khz fchop01 140 200 260 khz fchop10 420 600 780 khz fchop11 210 300 390 khz current setting reference volt ages vsen00 0.185 0.200 0.215 v vsen01 0.175 0.190 0.205 v vsen02 0.165 0.180 0.195 v vsen03 0.155 0.170 0.185 v vsen04 0.145 0.160 0.175 v vsen05 0.135 0.150 0.165 v vsen06 0.125 0.140 0.155 v vsen07 0.115 0.130 0.145 v vsen08 0.105 0.120 0.135 v vsen09 0.095 0.110 0.125 v vsen10 0.085 0.100 0.115 v vsen11 0.075 0.090 0.105 v vsen12 0.065 0.080 0.095 v vsen13 0.055 0.070 0.085 v vsen14 0.045 0.060 0.075 v vsen15 0.035 0.050 0.065 v pi (photo sensor driving transistor) output on-resistance ron i o = 10ma 1.5 2.5 ? output leakage current i o leak 1.0 ? a schmitt buffer logic input high-level voltage vinh bi1, bi2 0.5 ? v cc v logic input low-level voltage vinl bi1, bi2 0.25 ? v cc v * : design target value, not to be measured at production test.
lv8414cs no.a1868-3/36 package dimensions unit : mm (typ) 3406 pin assignment 0 0.8 1.0 0.2 0.4 0.6 1.2 80 0.52 1.00 85 60 20 40 0 100 --30 --20 pd max ? ta ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board : 40 50 0.8mm 3 glass epoxy four-layer board bi1 out1a pgnd1 pgnd2 out3a bi2 rf1 n.c scl sda sgnd rf3 out1b clk1 clk2 out3b out2a fr1 fr2 out4a rf2 ena v cc pi mo rf4 bo1 out2b vm1 vm2 out4b bo2 a b c d e f 123456 top view 654321 bottom view bi1 out1a pgnd1 pgnd2 out3a bi2 rf1 n.c scl sda sgnd rf3 out1b clk1 clk2 out3b out2a fr1 fr2 out4a rf2 ena v cc pi mo rf4 bo1 out2b vm1 vm2 out4b bo2 2.47 0.4 2.47 0.4 sanyo : wlp32j(2.47x2.47) side view top view side view bottom view 0.245 fedcba 0.65 max 0.175 2.47 2.47 1 2 3 4 5 6 0.4 0.235 0.235 0.4 0.42
lv8414cs no.a1868-4/36 block diagram microstep current setting microstep current setting output control logic out1b out1a vm1 rf1 ena sgnd + - + - + - clk1 out2b out2a excitation signal generator excitation signal generator monitor selector lvs circuit thermal shutdown circuit oscillator circuit i 2 c interface rf2 pgnd1 v cc rf4 rf3 pgnd2 + - start-up control block microstep current setting microstep current setting output control logic out3b out3a vm2 + - out4b out4a monitor selector + - bo2 bo1 v cc clk2 fr1 fr2 scl sda mo pi 30ma max bi1 bi2
lv8414cs no.a1868-5/36 pin functions pin no. pin name function equivalent circuit a1 a6 bi1 bi2 schmitt buffer input pin in v cc sgnd b3 scl i 2 c interface b4 sda i 2 c interface sda v cc sgnd e2 ena chip enable pin 100k in v cc sgnd c2 c5 clk1 clk2 step signal input pin d2 d5 fr1 fr2 forward/reverse rotation setting signal input pin a2 a5 c1 c6 d1 d6 f2 f5 out1a out3a out1b out3b out2a out4a out2b out4b h bridge output pin out vm rf b1 b6 e1 e6 rf1 rf3 rf2 rf4 current-sense resistor connection pins e5 mo monitor output pin out 500 v cc sgnd f1 f6 bo1 bo2 schmitt buffer output pin continued on next page.
lv8414cs no.a1868-6/36 continued from preceding page. pin no. pin name function equivalent circuit e4 pi photo sensor drive transistor output pin pi sgnd e3 v cc logic power supply connection pin b5 sgnd signal ground f3 f4 vm1 vm2 motor power supply connection pin a3 a4 pgnd1 pgnd2 power ground b2 n.c. unused pin
lv8414cs no.a1868-7/36 serial bus communication specifications i 2 c serial transfer timing conditions standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz data setup time ts1 setup time of scl with respect to the falling edge of sda 4.7 ? s ts2 setup time of sda with respect to the rising edge of scl 250 ns ts3 setup time of scl with respect to the rising edge of sda 4.0 ? s data hold time th1 hold time of scl with respect to the rising edge of sda 4.0 ? s th2 hold time of sda with respect to the falling edge of scl 0.08 ? s pulse width twl scl low period pulse width 4.7 ? s twh scl high period pulse width 4.0 ? s input waveform conditions ton scl, sda (input) rising time 1000 ? s tof scl, sda (input) falling time 300 ? s bus free time tbuf interval between stop condition and start condition 4.7 ? s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz data setup time ts1 setup time of scl with respect to the falling edge of sda 0.6 ? s ts2 setup time of sda with respect to the rising edge of scl 100 ns ts3 setup time of scl with respect to the rising edge of sda 0.6 ? s data hold time th1 hold time of scl with respect to the rising edge of sda 0.6 ? s th2 hold time of sda with respect to the falling edge of scl 0.08 ? s pulse width twl scl low period pulse width 1.3 ? s twh scl high period pulse width 0.6 ? s input waveform conditions ton scl, sda (input) rising time 300 ? s tof scl, sda (input) falling time 300 ? s bus free time tbuf interval between stop condition and start condition 1.3 ? s th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof
lv8414cs no.a1868-8/36 i 2 c bus transmission method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. when data is not being transferred, bo th scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. data transfer and acknowledgement response after the start condition is generated, data is transferred on e byte (8 bits) at a time. any number of data bytes can be transferred consecutively. an ack signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. the transmission of an ack signal is perform ed by setting the receiving side sda to low after sda at the sending side is released immediately after the clock pulse of sc l bit 8 in the data transferred has fallen low. after the receiving side has sent the ack signal, if the next byte transfer operation is to receive only the byte, the receiving side releases sda on the fa lling edge of the 9th clock of scl. there are no ce signals in the i 2 c bus ; instead, a 7-bit slave address is assi gned to each device, and the first byte of the transfer data is allocated to the 7- bit slave address and to the command (r /w) which specifies the direction of subsequent data transfer. the lv8414cs is a drive ic with a dedicated write function and it does not have a read function. the 7-bit address is transferred in se quence starting with msb, and the eighth bit is set to low. the second and subsequent bytes are transferred in write mode. in the lv8414cs, the slave address is stipulated to be ?1110010.?. ts2 th2 scl sda th1 ts3 scl sda start condition stop condition m s b l s b a c k l s b a c k m s b m s b l s b a c k w data 1 scl sda data slave address start stop 1100100 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
lv8414cs no.a1868-9/36 data transfer write format the slave address and write command must be allocated to the fi rst byte (8 bits) and the regi ster address in the ?serial data truth table? must be designated in the second byte. for the third byte, data transfer is carried out to the addr ess designated by the register address which is written in the second byte. subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. thus, continuous data transfer starting at th e designated address is made possible. when the register address is set to ? 00000011,? the address to which the next byte is transferred wraps around to "00000000." (1) data write example (2) actual example of continuous data transfer based on the ?serial data truth table? on the next page, the following settings are used for the actual example of the continuous data transfer shown in the above figure. (data transfer is set at the scl rising edge of ?d0? of each data.) 1/2-channel settings: output on, reset release, reverse (ccw) rotation, current reference voltage setting of 0.2v, no clk1 frequency division, 1-2 phase setting 3/4-channel settings: output on, reset release, forward (cw) rotation, current reference voltage setting of 0.2v, no clk2 frequency division, 1-2 phase setting other settings: 400khz chopping frequency, photo sensor off, mo output channels set to 1/2 channels, current reference voltage setting of 0.2v s s 1 1 1 0 0 1 0 0 a 0 0 0 0 0 0 0 1 a data 1 write data to register address 00000001 register address set (00000001) slave address start condition p stop condition master side transmission slave side transmission a acknowledge r/w = 0 written a data 2 a data 3 a data 4 write data to register address 00000000 write data to register address 00000011 write data to register address 00000010 a p 3/4-channel ? output on ? reset release ? forward rotation ? current reference volta g e 0.2v 1/2-channel ? clk1 frequency division ? 1-2 phase setting 3/4-channel ? clk2 frequency division ? 1-2 phase setting ? 400khz chopping ? photo sensor off ? mo output channels set to 1/2 channels ? mo output initial position 1/2-channel ? output on ? reset release ? reverse rotation ? current reference voltage 0.2v a7 a6 a5 a4 a3 a2 a1 a0 00000001 11100100 d7 d6 d5 d4 d3 d2 d1 d0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 01010000 d7 d6 d5 d4 d3 d2 d1 d0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 11001000 scl start stop sda m s b l s b m s b l s b m s b l s b m s b l s b m s b l s b m s b l s b a c k a c k a c k a c k a c k a c k w slave address register address data data data data
lv8414cs no.a1868-10/36 serial data truth table register address data setting mode set contents a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 * * * * 0 0 0 0 1/2ch current reference voltage setting 0.200v * * * * 0 0 0 1 0.190v * * * * 0 0 1 0 0.180v * * * * 0 0 1 1 0.170v * * * * 0 1 0 0 0.160v * * * * 0 1 0 1 0.150v * * * * 0 1 1 0 0.140v * * * * 0 1 1 1 0.130v * * * * 1 0 0 0 0.120v * * * * 1 0 0 1 0.110v * * * * 1 0 1 0 0.100v * * * * 1 0 1 1 0.090v * * * * 1 1 0 0 0.080v * * * * 1 1 0 1 0.070v * * * * 1 1 1 0 0.060v * * * * 1 1 1 1 0.050v * * * 0 * * * * 1/2ch excitation direction cw (forward rotation) * * * 1 * * * * ccw (reverse rotation) * * 0***** 1/2ch step/hold clear * * 1***** hold * 0 ****** 1/2ch counter reset reset * 1 ****** clear 0 * ****** 1/2ch output enable output off 1 * ****** output on 0 0 0 0 0 0 0 1 * * * * 0 0 0 0 3/4ch current reference voltage setting 0.200v * * * * 0 0 0 1 0.190v * * * * 0 0 1 0 0.180v * * * * 0 0 1 1 0.170v * * * * 0 1 0 0 0.160v * * * * 0 1 0 1 0.150v * * * * 0 1 1 0 0.140v * * * * 0 1 1 1 0.130v * * * * 1 0 0 0 0.120v * * * * 1 0 0 1 0.110v * * * * 1 0 1 0 0.100v * * * * 1 0 1 1 0.090v * * * * 1 1 0 0 0.080v * * * * 1 1 0 1 0.070v * * * * 1 1 1 0 0.060v * * * * 1 1 1 1 0.050v * * * 0 * * * * 3/4ch excitation direction cw (forward rotation) * * * 1 * * * * ccw (reverse rotation) * * 0***** 3/4ch step/hold clear * * 1***** hold * 0 ****** 3/4ch counter reset reset * 1 ****** clear 0 * ****** 3/4ch output enable output off 1 * ****** output on continued on next page.
lv8414cs no.a1868-11/36 continued from preceding page. register address data setting mode set contents a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 * * ****00 1/2ch clk1 division setting 1 (frequency division) * * ****01 1/2 * * ****10 1/4 * * ****11 1/8 * * * * 0 0 * * 3/4ch clk2 division setting 1 (frequency division) * * * * 0 1 * * 1/2 * * * * 1 0 * * 1/4 * * * * 1 1 * * 1/8 * * 0 0 * * * * 1/2ch excitation mode setting micro-step * * 0 1 * * * * 1-2 phase * * 1 0 * * * * 1-2 phase (full torque) * * 1 1 * * * * 2 phase 0 0 ****** 3/4ch excitation mode setting micro-step 0 1 ****** 1-2 phase 1 0 ****** 1-2 phase (full torque) 1 1 ****** 2 phase 0 0 0 0 0 0 1 1 * * ****00 chopping frequency setting 400khz * * ****01 200khz * * ****10 600khz * * ****11 300khz * * * * * 0 * * photo sensor driving off * * * * * 1 * * on * * * * 0 * * * mo output channel setting 1/2ch * * * * 1 * * * 3/4ch * * * 0 * * * * mo output position initial position * * * 1 * * * * 1-2 phase position * * ****** dummy data -
lv8414cs no.a1868-12/36 precautions for ic operations the supply voltage v cc , ena pin and i 2 c output on setting stand in the following relationship. ? v cc , ena pin, i 2 c output settings, and outputs (1) no output operations are performed unless the ena pin is set to high and the i 2 c output setting is set to on. (2) the i 2 c setting is accepted even if the ena pin is in low state. (other i 2 c settings are also accepted.) (3) when the supply voltage v cc is set to low, the internal data is reset. (the i 2 c output setting in the above figure is initialized to off state by the fall in the supply voltage v cc .) ena pin i 2 c output enable setting output l off setting high-impedance state h off setting high-impedance state l on setting high-impedance state h on setting output on state description of stepping motor drive operations the following state settings related to the control of the stepping motor are established using an i 2 c serial data communication. excitation mode : micro-step (256 divisions), 1-2 phase, 1-2 phase (full torque), or 2-phase excitation direction : cw (clockwise) or ccw (counterclockwise) step/hold : clear or hold counter reset : clear or reset output enable : output off or output on current setting reference voltage s : selects one of 16 values chopping frequency : selects one of 4 values 1. clk pin function clk input operating mode ena clk low * standby mode high excitation step proceeds high excitation step is kept the excitation steps are advanced by setting the clk1 (2) from low to high when the ena is in high state. vm v cc ena i 2 c output setting off(initial state) off(initial state) on setting on setting on setting on on on off setting off setting output (1) (2) (3)
lv8414cs no.a1868-13/36 2. initial position the excitation mode is set to the initial position when the ic is se t to the initial state at power-on or when the counter is reset. excitation mode initial position 1ch (3ch) 2ch (4ch) 256 divisions (16w1-2 phase) micro-step 100% 0% 1-2 phase 100% 0% 1-2 phase (full torque) 100% 0% 2 phase 100% -100% 3. mo pin function by setting the mo output channel and mo output position using the i 2 c serial data, the mo pin is set to low at the initial position in each excitation mode or at the 1-2 phase position in the micro-step drive mode. * it is assumed that the 1-2 phase setting for the mo output is used in the micro-step drive mode. even if the mo output position is set to 1-2 phase in the 1-2 phase or 2-phase mode, mo is set to low at the initial position and remains unchanged after it is initialized. * since the period during which mo is set to low extends from the rising edge of the clk which is the setting position, to the rising edge of the clk which moves to the next phase, care must be taken when a frequency division setting has been established. ena i 2 c serial data division setting 1 (frequency division) 1/2 setting mo 100% 100% -100% -100% 0% 0% i1 i2 clk1 (clk2)
lv8414cs no.a1868-14/36 4. excitation mode setting given below and in the following pages are the timing charts and monitor output pin mo signal in each excitation mode. [1-2 phase excitation timing chart] clk1 (clk2) ena mo 100% 100% -100% -100% 0% 0% 100% -100% 0% 2ch (4ch) current i1 i2 position number 1ch (3ch) current h
lv8414cs no.a1868-15/36 [1-2 phase excitation (full torque) timing chart] clk1 (clk2) ena mo 100% 100% -100% -100% 0% 0% 100% -100% 0% 2ch (4ch) current i1 i2 h position number 1ch (3ch) current
lv8414cs no.a1868-16/36 [2 phase excitation timing chart] clk1 (clk2) ena mo 100% 100% -100% -100% 0% 0% 100% -100% 0% 2ch (4ch) current i1 i2 h position number 1ch (3ch) current
lv8414cs no.a1868-17/36 [micro-step (16w1-2 phase excitation) timing chart] clk1 or clk2 ena h mo (initial) 100% expanded view -100% 0% 100% -100% 0% i1 i2 mo (1-2 phase)
lv8414cs no.a1868-18/36 5. switching the excitation mode during operation the timing at which the results of switching the excitatio n mode during operation are reflected and the position established after each excitation mode has been switched are as shown below. [timing at which the results of switching the excitation mode setting are reflected (from 1-2 phase to 2-phase)] the excitation mode switching is set at the rising edge of sclk (8th bit of sclk) of ?d0? and the setting is reflected starting with the next clk. i 2 c serial data excitation mode setting 1-2 phase setting 2 phase setting 1-2 phase setting 2 phase setting * 2-phase position numbers shown in parentheses expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data excitation mode setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs no.a1868-19/36 [positions when switching the excitation mode setting] (1) switching to the micro-step mode when operation has been switched from each excitation m ode to the micro-step mode, excitation position proceeds to the next micro step position by the first pulse generated after the switching. before switching the excitation mode step po sition after the excitation mode is switched excitation mode position 256 divisions micro-step micro-step ? 64 ? 63 to ? 33 ? 32 ? 31 to ? 1 ? 0 1-2 phase ? 64 ? 63 ? 32 ? 31 ? 0 - ? 1 1-2 phase full torque ? 64 ? 63 ? 32? ? 31 ? 0 - ? 1 2 phase ? 32? ? 31 100.0 66.7 33.3 2-channel phase current ratio (%) 1-channel phase current ratio (%) 0.0 33.3 66.7 100.0 32' (2 phase, 1-2 phase full torque) 30 - 1 62 34 1 64 31 0 32 33 63
lv8414cs no.a1868-20/36 (2) switching to the 1-2 phase excitation (1-2 phase excitation full torque) mode when operation has been switched from excitation mode to the 1-2 phase excitation (1-2 phase excitation full torque) mode, excitation position proceeds to position 32 ( 32?) by the first pulse generated after the switching, and then operation transfers to the 1-2 phase excitation (1-2 phase excitation full torque) mode. however, if the position established be fore the excitation mode switching is 32 ( 32?), excitation position proceeds to the next position in the 1-2 phase excitation (1-2 phase excitation full torque) mode by the first pulse generated after the switching. (3) switching to the 2-phase excitation mode if, in the case of channel 1 to chan nel 4, operation has been switched fro m each excitation mode to the 2-phase excitation mode, excitation position proceeds to position 32? by the first pulse generated after the switching, and then to the next position in the 2-phase excitation mode. before switching the excitation mode step po sition after the excitation mode is switched excitation mode position 1-2 phase 1-2 phase full torque 2 phase micro-step ? 64 ? 32 ? 32? ? 32? ? 63 to ? 33 ? 32 ? 32? ? 32? ? 32 ? 0 ? 0 ? 32? ? 31 to ? 1 ? 32 ? 32? ? 32? ? 0 - ? 32? - ? 32? - ? 32? 1-2 phase ? 64 ? 32? ? 32? ? 32 ? 0 ? 32? ? 0 - ? 32? - ? 32? 1-2 phase full torque ? 64 ? 32 ? 32? ? 32? ? 0 ? 32? ? 0 - ? 32 - ? 32? 2 phase ? 32? ? 0 ? 0( ? 0) 100.0 66.7 33.3 0.0 33.3 66.7 100.0 30 - 1 62 34 1 64 31 0 32 33 63 2-channel phase current ratio (%) 1-channel phase current ratio (%) 32' (2 phase, 1-2 phase full torque)
lv8414cs no.a1868-21/36 6. ena pin function and i 2 c serial data output enable setting [ena pin] v cc consumption current during standby can be reduced to virtually zero by setting the ena input pin to low. furthermore, when this pin is set to low, the output becomes off state (high-impedance), and the state of the internal logic circuit is set to the initial excitation position (initial position). by setting the ena pin to high, the output becomes on state, and the circuit operates from the initial excitation position. * the output does not operate unless ?output enab le? is set to the ?output on? state using an i 2 c serial data communication. [i 2 c serial data output enable setting] when ?output enable? is set to the ?outpu t off? state, the output is placed in th e high-impedance state at the rising edge of the 8th scl bit in the data transmission. however, since the internal logic circuit is activated, the position number advances if clk has been input. this means that when ?output enable? is set to the ?output on? state after this, the output is set to on at the rising edge of the 8th scl bit in the data transmission, and that the output level at this time will be the level at the number to which the position has advanced by the clk input. clk1 (clk2) ena output on output on output off i 2 c serial data communication enabled high-impedance state internal initial position 100% 100% -100% -100% 0% 0% i1 i2
lv8414cs no.a1868-22/36 [timing at which the output enable setting is reflected (output off)] the output enable setting is reflected at the rising edge of sclk (8th bit of sclk) of ?d0? i 2 c serial data output enable setting output on output off output on output off output on expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data output enable setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address high-impedance state high-impedance state
lv8414cs no.a1868-23/36 [timing at which the output enable setting is reflected (output on)] i 2 c serial data output enable setting output on output off output off output on output on expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data output enable setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address high-impedance state high-impedance state
lv8414cs no.a1868-24/36 7. fr pin function and i 2 c serial data excitation direction setting [fr pin] using the fr1 (fr2) forward/reverse rotation setting signal in put pin, it is possible to switch the excitation direction between forward and reverse rotation. when fr is set to low, the clockwise (cw: forward rotation) direction is set; conversely, when it is set to high, the counterclockwise (ccw: reverse rotation) direction is set. in cw (forward rotation) mode, the channel 2 (channel 4) current phase is delayed by 90 relative to the channel 1 (channel 3) current. in ccw (reverse rotation) mode, the channel 2 (channel 4) cu rrent phase is advanced by 90 relative to the channel 1 (channel 3) current. [i 2 c serial data excitation direction setting] when the excitation (rotation) direction of the stepping moto r is determined using the ?excitation direction? setting, the output is switched to forward or reverse rotation at the rising edge of the 8th bit of scl in the data transmission. in cw (forward rotation) mode, the channel 2 (channel 4) current phase is delayed by 90 relative to the channel 1 (channel 3) current. in ccw (reverse rotation) mode, the channel 2 (channel 4) cu rrent phase is advanced by 90 relative to the channel 1 (channel 3) current. * since the fr1 (fr2) forward/reverse signal input pins are provided with an internal pull-down resistor, these pins are set to the low state when they are open. furthermore, when these pins are set to low, the excitation direction setting established using an i 2 c serial data communication takes priority. conversely, when they are set to high, the excitation direction is always set to ?reverse rotation? regardless of the i 2 c communication setting. fr pin i 2 c excitation direction setting output l ccw (reverse rotation) reverse rotation direction h ccw (reverse rotation) reverse rotation direction l cw (forward rotation) forward rotation direction h cw (forward rotation) reverse rotation direction clk1 (clk2) fr1 (fr2) ena h cw (forward rotation) setting cw rotation ends. ccw rotation starts. ccw (reverse rotation) setting 100% 100% -100% -100% 0% 0% i1 i2
lv8414cs no.a1868-25/36 [timing at which excitation directi on setting is reflected (cw to ccw)] the excitation direction is set at the rising edge of sclk (8 th bit of sclk) of ?d0? and the setting is reflected starting with the next clk. i 2 c serial data excitation direction setting expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data excitation direction setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address cw (forward rotation) setting cw rotation ends. ccw rotation starts. ccw (reverse rotation) setting cw (forward rotation) setting cw rotation ends. ccw rotation starts. ccw (reverse rotation) setting
lv8414cs no.a1868-26/36 8. i 2 c serial data step/hold setting when the step/hold data is set to the hold state, the state of the external clock signal (clk) at that time is latched and held as the internal clock signal. since the state of clk (external) is low at the timing when step/hold is set for the first time as shown in the figure on the next page, the internal clk is held in the low state. in contra st, at the timing with which step/hold is set to the hold state for the second time, the internal clock si gnal will be held at the high level becau se the external clock (clk) was at the high level. when step/hold is set to the clear state, the internal cloc k is synchronized with the external clock (clk). the output holds the state it was in at the point step/hold is set to the hold state, and advances on the next clock signal rising edge after step/hold is set to the clear state. as long as step/hold is in the hold state, the position number does not advance even if an external clock (clk) signal is applied. internal clk "step/hold" setting signal clk (external) logic logic internal logic
lv8414cs no.a1868-27/36 [timing at which the step/hold setting is reflected (clear to hold)] the step/hold setting is reflected at the rising edge of sclk (8th bit of sclk) of ?d0? i 2 c serial data step/hold setting clear hold clear hold held at low level held at high level clear clear hold expanded clk1 (clk2) internal clock ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data excitation direction setting i 2 c serial data reflect timing clk1 (clk2) internal clock 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs no.a1868-28/36 [timing at which the step/hold setting is reflected (hold to clear)] i 2 c serial data step/hold setting clear hold hold clear held at low level held at high level clear clear hold expanded clk1 (clk2) internal clock ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data excitation direction setting i 2 c serial data reflect timing clk1 (clk2) internal clock 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs no.a1868-29/36 9. i 2 c serial data counter reset setting when ?counter reset? setting is set to the ?reset? state, the ou tput is set to the default state (initial position) at the risi ng edge of the 8th scl bit in the data transmission. when ?c ounter reset? setting is then set to the ?release? state, the position number of the output advances from the rising edge of the clk signal following the rising edge of the 8th scl bit in the data transmission. [timing at which the counter reset setting is reflected (clear to reset)] the counter reset setting is reflected at the rising edge of sclk (8th bit of sclk) of ?d0? i 2 c serial data counter reset setting clear clear clear reset clear reset expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data counter reset setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address initial position initial position
lv8414cs no.a1868-30/36 [timing at which the counter reset setting is reflected (reset to clear)] i 2 c serial data counter reset setting clear clear clear reset reset clear expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data counter reset setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address initial position initial position
lv8414cs no.a1868-31/36 10. number of divisions (i 2 c serial data frequency division setting) since this ic provides 256-division (16w1-2 phase) micro-step drive, a 32khz excitation step signal is required when driving a stepping motor at 1khz if 1-2 phase excitation is to be used. i 2 c communication allows one of four ratios, namely, 1 (no frequency division), 1/2, 1/4, or 1/8 to be selected as the clk frequency division ratio, so the motor speed can be set. [timing at which clk frequency division setting is reflected] the clk frequency division is set at the rising edge of sc lk (8th bit of sclk) of ?d0? and the setting is reflected starting with the next clk. i 2 c serial data frequency division setting 1 (no frequency division) 1/2 setting 1 (no frequency division) 1/2 setting expanded clk1 (clk2) ena h 100% 100% -100% -100% 0% 0% i1 i2 i 2 c serial data frequency division setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs no.a1868-32/36 11. output current reference voltage i 2 c communication allows the voltage to be switched to one of 16 steps from 0.200v to 0.050v. this is effective for reducing power consumption when stepping motor holding current is supplied. the output current is determined from the internal refe rence voltage and the resistance value connected between the current-sense resistor connection pin (rf) and gnd. the formula used to calculate the output current is given below. (output constant current) = (constant current reference voltage) (rf resistance value) example: with a 0.200v inte rnal reference voltage, 1.0 ? rf resistance and 100% current ratio iout = 0.2v ? 100% 1.0 ? = 200ma output current reference voltage values for 1/2 ch annels and 3/4 channels are set as shown below. 1/2 channels setting register address (a7 = ?0?, a6 = ?0?, a5 = ?0?, a4 = ?0?, a3 = ?0?, a2 = ?0 ?, a1 = ?0?, a0 = ?0?) 3/4 channels setting register address (a7 = ?0?, a6 = ?0?, a5 = ?0?, a4 = ?0?, a3 = ?0?, a2 = ?0 ?, a1 = ?0?, a0 = ?1?) d3 d2 d1 d0 current se tting reference voltage 0 0 0 0 0.200v 0 0 0 1 0.190v 0 0 1 0 0.180v 0 0 1 1 0.170v 0 1 0 0 0.160v 0 1 0 1 0.150v 0 1 1 0 0.140v 0 1 1 1 0.130v 1 0 0 0 0.120v 1 0 0 1 0.110v 1 0 1 0 0.100v 1 0 1 1 0.090v 1 1 0 0 0.080v 1 1 0 1 0.070v 1 1 1 0 0.060v 1 1 1 1 0.050v
lv8414cs no.a1868-33/36 [timing at which current setting re ference voltage is reflected] the current setting reference voltage is reflected at the rising edge of sclk (8th bit of sclk) of ?d0? example: with 1.0 ? for rf and 100% current ratio i 2 c serial data current reference voltage setting 0.2v setting 0.1v setting 0.2v setting 0.1v setting expanded clk1 (clk2) ena h l 200ma iout 100ma 0ma i 2 c serial data current reference voltage setting 200ma iout 100ma 0ma i 2 c serial data reflect timing scl start stop data sda a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs no.a1868-34/36 12. current control operation specification [sine wave increasing direction] [sine wave increasing direction] [description of current limiting operation] in each current mode, the operation sequence is as described below : at rise of chopping frequency, the charge mode begins. ? the coil current (icoil) and settin g current (iref) are compared in the forced charge section. when (icoil ? iref) existed in the forced charge section: the charge mode is established until icoil ? iref. then it is switched to the slow decay mode, and finally it is switched to the fast decay mode. when (icoil ? iref) did not exist in the forced charge section: the fast decay mode begins. the coil current is attenuated in the fast decay mode till one cycle of chopping is over. above operations are repeated. normally , the slow (+fast) decay mode continues in the sine wave increasing direction, then entering the fast decay mode till the curren t is attenuated to the set level and followed by the slow decay mode. (charge mode) (slow decay mode) (fast decay mode) fast slow charge fast slow charge current mode fchop (initial state: 400khz) coil current clk set current set current forced charge section fast slow fast slow charge current mode fchop (initial state: 400khz) coil current clk set current set current forced charge section forced charge section charge vm on off off on vm on off off on vm off on off on
lv8414cs no.a1868-35/36 [timing at which the chopping frequency setting is reflected (400khz to 200khz)] the frequency setting is reflected at the rising edge of sclk (8th bit of sclk) of ?d0? i 2 c serial data chopping frequency setting 400khz setting 200khz setting 400khz setting 200khz setting expanded clk1 (clk2) ena h 100% 100% -100% -100% chopping frequency chopping frequency 0% 0% i1 i2 i 2 c serial data division setting i 2 c serial data reflect timing clk1 (clk2) 100% scl start stop data sda 100% -100% -100% 0% 0% i1 i2 a7 a6 a5 a4 a3 a2 a1 a0 11100100 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b a c k a c k a c k w slave address m s b l s b m s b l s b register address
lv8414cs ps no.a1868-36/36 this catalog provides information as of august, 2012. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.

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